1. Field of Invention
This invention relates in general to a semiconductor isolation method, and more particularly to a method for forming a shallow trench isolation.
2. Description of Related Art
To prevent short circuiting and unnecessary operational interference between transistors in the manufacturing of semiconductors, it is often necessary to isolate every single transistor. As the level of integration in integrated circuits has become higher and higher, for example, a hundred thousand of more transistors can easily be packed inside 1.about.2 cm.sup.2 of silicon surface area in more advanced VLSI manufacturing processes, a conventional isolation method such as local oxidation method (LOCOS) has become inadequate. LOCOS is now gradually being replaced by shallow trench isolation methods, which require less space for the isolation regions and hence are capable of increasing the level of component integration. The shallow trench method includes literally "digging" a trench in areas between two transistors by an anisotropic dry etching method and then refilling the trench with insulating material such as silicon dioxide to achieve an effective isolation.
A conventional method for forming a shallow trench isolation is to form sequentially a pad oxide layer and a silicon nitride layer above a semiconductor substrate, then using photolithographic and etching techniques to define a window in the location designed for the formation of a shallow trench isolation region. Next, using the silicon nitride layer as a mask, the substrate surface exposed through the window is etched to form a shallow trench for the necessary isolation. Details of the manufacturing steps are shown in FIGS. 1A through ID.
First, referring to FIG. 1A, a pad oxide layer 102 with a thickness of about 20 nm and a polishing barrier stop layer 104, such as silicon nitride, with a thickness of about 200 nm are formed sequentially above a semiconductor substrate 100. Next, photolithographic processes are used to define a photoresist layer 106. With the photoresist layer 106 in place, the polishing barrier stop layer 104, the pad oxide layer 102 and the semiconductor substrate 100 are etched sequentially to form at least one narrow trench 101 and at least one wide trench 103 having a width, for example, slightly bigger than about 3 .mu.m. The depth of the trenches below the surface of the semiconductor substrate 100 is about 400 nm.
Referring next to FIG. 1B, after the removal of photoresist layer 106, a liner oxide layer (not shown in the Figure) is formed on the exposed substrate surface of trenches 101 and 103 by a thermal oxidation method. Then, a dielectric layer 108 is deposited to refill the narrow trenches 101 and the wide trench 103 as in FIG. 1A, for example, by a semi-atmospheric chemical vapor deposition (SACVD) method using tetra-ethyl-ortho-silicate (TEOS)/Ozone (O.sub.3) as the main reactive gases to deposit a silicon dioxide layer. However, a slightly caved-in region 105 is created on the upper surface of the dielectric layer 108 above the wide trench 103. The step height of the caved-in region 105 can be comparable to the depth of the trenches itself Referring next to FIG. 1C, planarization is subsequently performed using a chemical-mechanical polishing (CMP) method to remove part of the dielectric layer 108 and part of the polishing barrier stop layer 104. However, due to the effects of a pattern density variation in the wafer as well as the aforementioned caved-in region 105 on the upper surface above the wide trenches, the polishing rate for each region is going to be different. Generally, for regions having less polishing barrier stop such as 108b, overpolishing will result, forming a slightly concave surface 107 known as dishing.
Lastly, referring to Figure ID, the residual polishing barrier stop layer 104 and the pad oxide layer 102 are removed, thus finishing the formation of the shallow trench isolation regions. Yet, problems generated by the dishing effect still remain. Since the upper surface of the wide trenches slightly sags in the middle, out of focus problems will arise in subsequent photolithographic operations, and as a result, subsequent etching for the manufacturing of the gate terminals will be affected.